EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

Algorithms go from floating- to fixed-point

Migrating signal-processing algorithms from floating- to fixed-point is often necessary to meet various design constraints, including real-time performance, cost and power dissipation. The migration ...
Design-Reuse

Implementing matrix inversions in fixed-point hardware

We implement fixed-point matrix inversion on a Virtex-4 FPGA using a synthesizable QR-decomposition MATLAB model and the AccelDSP Synthesis tool. The resulting function occupies 12% of a XC4VSX55 ...
New Electronics

Floating point enabled microcontrollers in embedded designs

Floating point units (fpu) can increase the range and precision of mathematical calculations or enable greater throughput in less time, making it easier to meet real time requirements. Or, by enabling ...
Design-Reuse

Using FPGAs to Improve the Performance of Radar, Navigation and Guidance Systems

Radar, navigation and guidance systems process data that is acquired using arrays of sensors. The energy delta from sensor to sensor over time holds the key to information such as targets, position or ...