EDN

SystemVerilog won’t cause incompatible standards

In an EDA Views column posted to EEdesign April 4, 2003, Mitch Weaver of Cadence Design Systems wrote of the need to extend the Verilog standard to support ever-increasing design sizes. Mr. Weaver ...
EDN

Commentary: SystemVerilog enables design with verification

The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...
Design-Reuse

Randsequence: SystemVerilog's unsung hero

Constrained random verification, for quite some time now, has been the default verification methodology for complex ASIC/SoC designs. Central to this methodology is the process of letting the ...
Electronic Design

Simulator Adds Assertion IP And Native SystemVerilog Support

The latest release of the VCS verification environment sports new capabilities that help users find more bugs more quickly, with up to a fivefold increase in verification speed (see the figure). Key ...
Business Wire

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMe TM SSD and PCIe® designs using ...
Electronic Design

Cadence, Mentor Team To Open Up SystemVerilog Verification

When the SystemVerilog hardware description language (HDL) came onto the scene a few years ago, it promised true openness and interoperability. Here, crowed the hype, was an HDL that would enable ...